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| STG4259 Low voltage 0.3 max dual SPDT switch with break-before-make feature and 15KV ESD protection Features Wide operating voltage range: VCC (Opr) = 1.65 V to 4.8 V Low power dissipation: ICC = 0.2 A (max) at TA = 85C Low ON resistance VIN = 0V: - RON = 0.4 (max TA = 25C) at VCC = 2.25 V - RON = 0.35 (max TA = 25C) at VCC = 3.0 V - RON = 0.30 (max TA = 25C) at VCC = 4.3 V Separate supply voltage for switch and control pin Separate control pin for each switch Latch-up performance exceeds 100 mA per JESD 78, class II ESD performance tested on common channels (D1 and D2 pins) - 9 kV IEC-61000-4-2 ESD, contact discharge - 15 kV IEC-61000-4-2 ESD, air gap discharge ESD performance tested on all other pins - 8 kV IEC-61000-4-2 ESD, contact discharge - 500 V machine model (JESD22 A115-A) - 1500 V charged-device model (JESD22 C101) - 8 kV IEC-61000-4-2 ESD, air gap discharge Flip-Chip11 Description The STG4259 is a high-speed CMOS low voltage dual analog SPDT (single pole dual throw) switch or 2:1 multiplexer/ demultiplexer switch fabricated in silicon gate C2MOS technology. It is designed to operate from 1.65 V to 4.8 V, making this device ideal for portable applications. It offers low ON resistance (0.30 ) at VCC = 4.3 V. The SEL inputs are provided to control the switches. The switch S1 is ON (connected to common port D) when the SEL input is held high and OFF (high impedance state exists between the two ports) when SEL is held low; the switch S2 is ON (it is connected to common port D) when the SEL input is held low and OFF (high impedance state exist between the two ports) when SEL is held high. Additional key features are fast switching speed, break-before-make delay time and ultra low power consumption. All inputs and outputs are equipped with protection circuits against static discharge, giving them ESD immunity and transient excess voltage. Table 1. Device summary Order code STG4259BJR Package Flip-Chip11 Packing Tape and Reel August 2007 Rev 4 1/19 www.st.com Contents STG4259 Contents 1 2 3 4 5 6 Logic diagram and pin-out information . . . . . . . . . . . . . . . . . . . . . . . . . 3 Maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Test circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 2/19 STG4259 Logic diagram and pin-out information 1 Logic diagram and pin-out information Figure 1. Functional diagram SEL1 D1 1S1 1S2 2S1 2S2 D2 SEL2 Figure 2. Input equivalent circuit SEL SEL Table 2. Truth table SELn H L Switch nS1 ON OFF (1) Switch nS2 OFF (1) ON 1. High impedance 3/19 Logic diagram and pin-out information Figure 3. Pin connection (bump side view) STG4259 Flip-Chip11 Table 3. Pin description Flip-Chip11 4, 10, 6, 12 9, 7 3, 1 11 2 5 Symbol 1S1, 1S2, 2S1, 2S2 D1, D2 SEL1, SEL2 VCC VL GND Name and function Independent channels Common channels Control Positive supply voltage Logic supply voltage Ground (0V) 4/19 STG4259 Maximum rating 2 Maximum rating Stressing the device above the rating listed in the "Absolute Maximum Ratings" table may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other relevant quality documents. Table 4. Symbol VCC VL VI VIC VO IIKC IIK IOK IO IOP ICC or IGND PD Tstg TL 1. Absolute maximum ratings Parameter Supply voltage Logic supply voltage DC input voltage DC control input voltage DC output voltage DC input diode current on control pin (VSEL< 0V) DC input diode current (VSEL< 0V) DC output diode current DC output current DC output current peak (pulse at 1ms, 10% duty cycle) DC VCC or ground current Power dissipation at TA = 70C (1) Storage temperature Lead temperature (10 sec) Value -0.5 to 5.5 -0.5 to 5.5 -0.5 to VCC + 0.5 -0.5 to VL + 0.5 -0.5 to VCC + 0.5 - 50 50 20 300 500 100 500 -50 to 105 260 Unit V V V V V mA mA mA mA mA mA mW C C Derate above 70C by 18.5mW/C 5/19 Maximum rating Table 5. Symbol VCC VL VI VIC VO Top Supply voltage STG4259 Recommended operating conditions Parameter (1) Value 1.65 to 4.8 1.65 to VCC 0 to VCC 0 to VL 0 to VCC -40 to 85 0 to 20 Unit V V V V V C Logic supply voltage Input voltage Control input voltage Output voltage Operating temperature VL = 1.65 V to Input rise and fall time control 2.7 V input VL = 3.0 to 4.8 V dt/dv ns/V 0 to 10 1. Truth table guaranteed: 1.65 V to 4.8 V 6/19 STG4259 Electrical characteristics 3 Electrical characteristics Table 6. DC specifications Test conditions Symbol Parameter VCC (V) VL (V) Min 1.65 - 1.95 VIH High level input voltage 1.65 4.3 2.3 - 2.7 3.0 - 3.6 4.3 1.65 - 1.95 VIL Low level input voltage 1.65 4.3 2.3 - 2.7 3.0 - 3.6 4.3 1.8 2.25 RON ON resistance 3 3.7 4.3 1.8 ON resistance match between channels (1) 2.25 3 3.7 4.3 1.8 2.5 RFLAT ON resistance flatness (2) 3 3.7 4.3 Sn OFF state leakage current Sn ON state leakage current 1.65 4.8 VS = 0 to VCC 1.65 - 4.8 VD = 0 to VCC VS = 0 to 1.65 - 4.8 VCC VD = open VS = 0 V to 1.65 - 4.8 VCC IS = 100 mA VS = 0 V to 1.65 - 4.8 VCC IS = 100 mA VS = 0 V to 1.65 - 4.8 VCC IS = 100 mA 1.25 1.75 2.35 2.8 0.6 0.8 1.05 1.5 0.49 0.65 0.30 0.40 0.25 0.35 0.22 0.32 0.21 0.30 5 3 3 3 3 300 130 90 90 90 400 170 120 120 120 450 230 170 170 170 m m Typ Max Min 1.25 1.75 V 2.35 2.8 0.6 0.8 V 1.05 1.5 0.85 0.50 0.45 0.42 0.40 Max Value TA = 25C -40 to 85C Unit RON IOFF -20 20 -300 300 nA ION 1.65 4.8 -20 20 -100 100 nA 7/19 Electrical characteristics Table 6. ID STG4259 DC specifications (continued) D ON state leakage current Quiescent supply current SEL leakage current 1.65 4.8 1.654.8 1.654.8 VS = open 1.65 - 4.8 VD = 0 to VCC 1.65 - 4.8 1.65 - 4.8 VSEL= VCC or GND VSEL= 4.3V or GND -20 0.05 -0.1 20 -100 100 nA ICC ISEL 0.05 0.1 -0.2 -1 0.2 1 A A 1. RON = RON(Max) - RON(Min) 2. Flatness is defined as the difference between the maximum and minimum value of on resistance as measured over the specified analog signal ranges. Table 7. ) AC electrical characteristics (CL = 35 pF, RL = 50 tr = tf 5 ns) , Test conditions Value TA = 25C Min Typ 0.13 1.65 4.8 0.15 0.16 0.16 95 1.65 4.8 VS = VCC RL = 50 CL = 30 pF 48 33 29 12 1.65 4.8 VS = VCC RL = 50 CL = 30 pF 12 13 13 10 1.65 4.8 CL = 35 pF RL = 50 VS = VCC/2 10 10 10 66 28 18 12 86 1.654.8 CL = 1nF VGEN = 0V 95 98 103 pC ns 123 62 43 38 15 16 17 17 95 70 55 40 70 55 40 35 ns ns ns Max -40 to 85C Min Max Uni t Symbol Parameter VCC (V) 1.65 1.95 VL (V) tPLH, tPHL Propagation delay 2.3 - 2.7 3.0 - 3.3 3.6 - 4.3 1.65 1.95 tON Turn-ON time 2.3 - 2.7 3 - 3.6 4.3 1.65 1.95 tOFF Turn-OFF time 2.3 - 2.7 3 - 3.6 4.3 1.65 1.95 tD Breakbefore-make time delay 2.3 - 2.7 3 - 3.6 4.3 1.651.95 Q Charge injection 2.3-2.7 3.0-3.3 3.6-4.3 8/19 STG4259 Table 8. ) Electrical characteristics Analog switch characteristics (CL = 5pF, RL = 50, TA = 25C) Test conditions Symbol Parameter VCC (V) OIRR Xtalk OFF isolation (1) Crosstalk 1.65 4.3 1.6 - 4.3 VL (V) 4.3 4.3 VS = 1VRMS f = 100kHz VS = 1VRMS f = 100 kHz RL = 600 CL = 50 pF VS = VCC VPP f = 600Hz to 20 kHz RL = 50 Value TA = 25C Min Typ -71 -93 Max -40 to 85C Unit Min Max dB dB THD Total harmonic distortion 2.3 - 4.3 4.3 0.01 % BW -3dB bandwidth (switch ON) Control pin input capacitance Sn port capacitance D port capacitance when switch is enabled 1.65 4.3 4.3 40 MHz CSEL 1.8 - 4.3 1.8 4.3 1.8 4.3 1.8 4.3 VL = VCC 30 pF CSn 1.8 - 4.3 VL = VCC 95 pF CD 1.8 - 4.3 VL = VCC 230 pF 1. OFF-isolation = 20 log10 (VD/VS), VD = output, VS = input to off switch 9/19 Test circuits STG4259 4 Figure 4. Test circuits ON resistance Figure 5. Bandwidth Figure 6. OFF leakage Figure 7. Channel-to-channel crosstalk Figure 8. OFF isolation 10/19 STG4259 Figure 9. Test circuit Test circuits Note: 1 2 3 CL = 5/35pF or equivalent: (includes jig capacitance) RL = 50 or equivalent RT = ZOUT of pulse generator (typically 50) Figure 10. Break-before-make time delay 11/19 Test circuits Figure 11. Switching time and charge injection (VGEN = 0V, RGEN = 0, RL = 1M CL = 100pF) , STG4259 Figure 12. Turn ON, turn OFF delay time 12/19 STG4259 Package mechanical data 5 Package mechanical data In order to meet environmental requirements, ST offers these devices in ECOPACK(R) packages. These packages have a Lead-free second level interconnect. The category of second Level Interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. ECOPACK is an ST trademark. ECOPACK specifications are available at: www.st.com. Figure 13. Flip-Chip11 package outline 1. Drawing not to scale. 13/19 Package mechanical data Table 9. Dim. Min A A1 A2 b D D1 E E1 e f ccc 0.45 2.018 0.265 1.518 0.585 0.21 Typ 0.65 0.25 0.4 0.315 1.568 1 2.068 1.5 0.5 0.284 0.08 0.55 2.118 0.365 1.618 Max 0.715 0.29 Min 0.60 0.22 0.38 0.290 1.553 0.99 2.083 1.49 0.46 0.272 Typ 0.65 0.25 0.4 0.315 1.568 1 2.068 1.5 0.5 0.284 0.08 STG4259 Flip-Chip11 mechanical data Data book (mm) Drawing (mm) Max 0.70 0.28 0.42 0.340 1.583 1.01 2.118 1.51 0.54 0.292 The terminal A1 on the bumps side is identified by a distinguishing feature (for instance by a circular "clear area" - typically 0.1 mm diameter) and/or a missing bump. The terminal A1 on the backside of the product is identified by a distinguishing feature (for instance by a circular "dot" - typically 0.5 mm diameter). Figure 14. Foot print recommendations 14/19 STG4259 Figure 15. Marking Package mechanical data Dot, ST logo S2 = marking V = manufacturing Location yww = datecode (y = year, ww = week) S2V YWW Figure 16. Flip-Chip11 tape specification 15/19 Package mechanical data Figure 17. Flip-Chip11 reel information STG4259 16/19 STG4259 Figure 18. Flip-Chip11 reel for carrier tape information Package mechanical data 17/19 Revision history STG4259 6 Revision history Table 10. Date 03-Oct-2006 16-Oct-2006 07-Aug-2007 28-Aug-2007 Document revision history Revision 1 2 3 4 First release Schematic Figure 1 on page 3 updated Air discharge ESD rating updated Changed Figure 16 on page 15 Changes 18/19 STG4259 Please Read Carefully: Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries ("ST") reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice. All ST products are sold pursuant to ST's terms and conditions of sale. Purchasers are solely responsible for the choice, selection and use of the ST products and services described herein, and ST assumes no liability whatsoever relating to the choice, selection or use of the ST products and services described herein. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted under this document. If any part of this document refers to any third party products or services it shall not be deemed a license grant by ST for the use of such third party products or services, or any intellectual property contained therein or considered as a warranty covering the use in any manner whatsoever of such third party products or services or any intellectual property contained therein. UNLESS OTHERWISE SET FORTH IN ST'S TERMS AND CONDITIONS OF SALE ST DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY WITH RESPECT TO THE USE AND/OR SALE OF ST PRODUCTS INCLUDING WITHOUT LIMITATION IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE (AND THEIR EQUIVALENTS UNDER THE LAWS OF ANY JURISDICTION), OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT. 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The ST logo is a registered trademark of STMicroelectronics. All other names are the property of their respective owners. (c) 2007 STMicroelectronics - All rights reserved STMicroelectronics group of companies Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States of America www.st.com 19/19 |
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